1 ;-------------------------------------------------------- 2 ; File Created by SDCC : FreeWare ANSI-C Compiler 3 ; Version 2.3.3 Sun Oct 14 14:31:04 2007 4 5 ;-------------------------------------------------------- 6 .module 1 7 8 ;-------------------------------------------------------- 9 ; Public variables in this module 10 ;-------------------------------------------------------- 11 .globl _main 12 .globl _czekaj 13 ;-------------------------------------------------------- 14 ; special function registers 15 ;-------------------------------------------------------- 16 ;-------------------------------------------------------- 17 ; special function bits 18 ;-------------------------------------------------------- 00B4 19 _t1 = 0x00b4 20 ;-------------------------------------------------------- 21 ; overlayable register banks 22 ;-------------------------------------------------------- 23 .area REG_BANK_0 (REL,OVR,DATA) 0000 24 .ds 8 25 ;-------------------------------------------------------- 26 ; internal ram data 27 ;-------------------------------------------------------- 28 .area DSEG (DATA) 29 ;-------------------------------------------------------- 30 ; overlayable items in internal ram 31 ;-------------------------------------------------------- 32 .area OSEG (OVR,DATA) 33 ;-------------------------------------------------------- 34 ; Stack segment in internal ram 35 ;-------------------------------------------------------- 36 .area SSEG (DATA) 0000 37 __start__stack: 0000 38 .ds 1 39 40 ;-------------------------------------------------------- 41 ; indirectly addressable internal ram data 42 ;-------------------------------------------------------- 43 .area ISEG (DATA) 44 ;-------------------------------------------------------- 45 ; bit data 46 ;-------------------------------------------------------- 47 .area BSEG (BIT) 48 ;-------------------------------------------------------- 49 ; external ram data 50 ;-------------------------------------------------------- 51 .area XSEG (XDATA) 52 ;-------------------------------------------------------- 53 ; external initialized ram data 54 ;-------------------------------------------------------- 55 .area XISEG (XDATA) 56 ;-------------------------------------------------------- 57 ; interrupt vector 58 ;-------------------------------------------------------- 59 .area CSEG (CODE) 0000 60 __interrupt_vect: 0000 02s00r00 61 ljmp __sdcc_gsinit_startup 0003 32 62 reti 0004 63 .ds 7 000B 32 64 reti 000C 65 .ds 7 0013 32 66 reti 0014 67 .ds 7 001B 32 68 reti 001C 69 .ds 7 0023 32 70 reti 0024 71 .ds 7 002B 32 72 reti 002C 73 .ds 7 74 ;-------------------------------------------------------- 75 ; global & static initialisations 76 ;-------------------------------------------------------- 77 .area GSINIT (CODE) 78 .area GSFINAL (CODE) 79 .area GSINIT (CODE) 0000 80 __sdcc_gsinit_startup: 0000 75 81rFF 81 mov sp,#__start__stack - 1 0003 12s00r00 82 lcall __sdcc_external_startup 0006 E5 82 83 mov a,dpl 0008 60 03 84 jz __sdcc_init_data 000A 02s00r33 85 ljmp __sdcc_program_startup 000D 86 __sdcc_init_data: 87 ; _mcs51_genXINIT() start 000D 74r00 88 mov a,#l_XINIT 000F 44s00 89 orl a,#l_XINIT>>8 0011 60 29 90 jz 00003$ 0013 74r00 91 mov a,#s_XINIT 0015 24r00 92 add a,#l_XINIT 0017 F9 93 mov r1,a 0018 74s00 94 mov a,#s_XINIT>>8 001A 34s00 95 addc a,#l_XINIT>>8 001C FA 96 mov r2,a 001D 90s00r00 97 mov dptr,#s_XINIT 0020 78r00 98 mov r0,#s_XISEG 0022 75 A0s00 99 mov p2,#(s_XISEG >> 8) 0025 E4 100 00001$: clr a 0026 93 101 movc a,@a+dptr 0027 F2 102 movx @r0,a 0028 A3 103 inc dptr 0029 08 104 inc r0 002A B8 00 02 105 cjne r0,#0,00002$ 002D 05 A0 106 inc p2 002F E5 82 107 00002$: mov a,dpl 0031 B5 01 F1 108 cjne a,ar1,00001$ 0034 E5 83 109 mov a,dph 0036 B5 02 EC 110 cjne a,ar2,00001$ 0039 75 A0 FF 111 mov p2,#0xFF 003C 112 00003$: 113 ; _mcs51_genXINIT() end 114 .area GSFINAL (CODE) 0000 02s00r33 115 ljmp __sdcc_program_startup 116 ;-------------------------------------------------------- 117 ; Home 118 ;-------------------------------------------------------- 119 .area HOME (CODE) 120 .area CSEG (CODE) 121 ;-------------------------------------------------------- 122 ; code 123 ;-------------------------------------------------------- 124 .area CSEG (CODE) 0033 125 __sdcc_program_startup: 0033 12s00r3D 126 lcall _main 127 ; return from main will lock up 0036 80 FE 128 sjmp . 129 ;------------------------------------------------------------ 130 ;Allocation info for local variables in function 'czekaj' 131 ;------------------------------------------------------------ 132 ;------------------------------------------------------------ 133 ;1.c:3: void czekaj(void) 134 ; ----------------------------------------- 135 ; function czekaj 136 ; ----------------------------------------- 0038 137 _czekaj: 0002 138 ar2 = 0x02 0003 139 ar3 = 0x03 0004 140 ar4 = 0x04 0005 141 ar5 = 0x05 0006 142 ar6 = 0x06 0007 143 ar7 = 0x07 0000 144 ar0 = 0x00 0001 145 ar1 = 0x01 146 ;1.c:6: for (i = 0; i<100; i++); 147 ; genAssign 0038 7A 64 148 mov r2,#0x64 003A 149 00103$: 150 ; genDjnz 151 ; Peephole 132 changed ljmp to sjmp 152 ; Peephole 205 optimized misc jump sequence 003A DA FE 153 djnz r2,00103$ 003C 154 00108$: 003C 155 00109$: 003C 156 00104$: 003C 22 157 ret 158 ;------------------------------------------------------------ 159 ;Allocation info for local variables in function 'main' 160 ;------------------------------------------------------------ 161 ;glosnik Allocated to registers r2 162 ;------------------------------------------------------------ 163 ;1.c:9: void main(void) 164 ; ----------------------------------------- 165 ; function main 166 ; ----------------------------------------- 003D 167 _main: 168 ;1.c:11: unsigned char glosnik = 0; 169 ; genAssign 003D 7A 00 170 mov r2,#0x00 003F 171 00105$: 172 ;1.c:14: if (glosnik == 0) 173 ; genCmpEq 174 ; Peephole 132 changed ljmp to sjmp 175 ; Peephole 199 optimized misc jump sequence 003F BA 00 06 176 cjne r2,#0x00,00102$ 177 ;00111$: 178 ; Peephole 200 removed redundant sjmp 0042 179 00112$: 180 ;1.c:16: glosnik = 1; 181 ; genAssign 0042 7A 01 182 mov r2,#0x01 183 ;1.c:17: t1 = 1; 184 ; genAssign 0044 D2 B4 185 setb _t1 186 ; Peephole 132 changed ljmp to sjmp 0046 80 04 187 sjmp 00103$ 0048 188 00102$: 189 ;1.c:19: glosnik = 0; 190 ; genAssign 0048 7A 00 191 mov r2,#0x00 192 ;1.c:20: t1 = 0; 193 ; genAssign 004A C2 B4 194 clr _t1 004C 195 00103$: 196 ;1.c:22: czekaj(); 197 ; genCall 004C C0 02 198 push ar2 004E 12s00r38 199 lcall _czekaj 0051 D0 02 200 pop ar2 201 ; Peephole 132 changed ljmp to sjmp 0053 80 EA 202 sjmp 00105$ 0055 203 00107$: 0055 22 204 ret 205 .area CSEG (CODE) 206 .area XINIT (CODE)