Project Information c:\temp\cw2_5.rpt MAX+plus II Compiler Report File Version 10.2 07/10/2002 Compiled: 10/14/2007 12:03:21 Copyright (C) 1988-2002 Altera Corporation Any megafunction design, and related net list (encrypted or decrypted), support information, device programming or simulation file, and any other associated documentation or information provided by Altera or a partner under Altera's Megafunction Partnership Program may be used only to program PLD devices (but not masked PLD devices) from Altera. Any other use of such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information is prohibited for any other purpose, including, but not limited to modification, reverse engineering, de-compiling, or use with any other silicon devices, unless such use is explicitly licensed under a separate agreement with Altera or a megafunction partner. Title to the intellectual property, including patents, copyrights, trademarks, trade secrets, or maskworks, embodied in any such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information provided by Altera or a megafunction partner, remains with Altera, the megafunction partner, or their respective licensors. No other licenses, including any licenses needed under any third party's intellectual property, are provided herein. ***** Project compilation was successful Untitled ** DEVICE SUMMARY ** Chip/ Input Output Bidir Shareable POF Device Pins Pins Pins LCs Expanders % Utilized cw2_5 EPM7032LC44-6 11 1 0 1 8 3 % User Pins: 11 1 0 Device-Specific Information: c:\temp\cw2_5.rpt cw2_5 ***** Logic for device 'cw2_5' compiled without errors. Device: EPM7032LC44-6 Device Options: Turbo Bit = ON Security Bit = OFF R E S E R V G G G G G V d d a C N N N N N E 6 7 0 C D D D D D y D -----------------------------------_ / 6 5 4 3 2 1 44 43 42 41 40 | d5 | 7 39 | RESERVED d4 | 8 38 | RESERVED d3 | 9 37 | RESERVED GND | 10 36 | RESERVED d2 | 11 35 | VCC d1 | 12 EPM7032LC44-6 34 | RESERVED d0 | 13 33 | RESERVED a2 | 14 32 | RESERVED VCC | 15 31 | RESERVED a1 | 16 30 | GND RESERVED | 17 29 | RESERVED |_ 18 19 20 21 22 23 24 25 26 27 28 _| ------------------------------------ R R R R G V R R R R R E E E E N C E E E E E S S S S D C S S S S S E E E E E E E E E R R R R R R R R R V V V V V V V V V E E E E E E E E E D D D D D D D D D N.C. = No Connect. This pin has no internal connection to the device. VCC = Dedicated power pin, which MUST be connected to VCC. GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND. RESERVED = Unused I/O pin, which MUST be left unconnected. Device-Specific Information: c:\temp\cw2_5.rpt cw2_5 ** RESOURCE USAGE ** Shareable External Logic Array Block Logic Cells I/O Pins Expanders Interconnect A: LC1 - LC16 0/16( 0%) 11/16( 68%) 0/16( 0%) 0/36( 0%) B: LC17 - LC32 1/16( 6%) 1/16( 6%) 8/16( 50%) 11/36( 30%) Total dedicated input pins used: 0/4 ( 0%) Total I/O pins used: 12/32 ( 37%) Total logic cells used: 1/32 ( 3%) Total shareable expanders used: 8/32 ( 25%) Total Turbo logic cells used: 1/32 ( 3%) Total shareable expanders not available (n/a): 0/32 ( 0%) Average fan-in: 11.00 Total fan-in: 11 Total input pins required: 11 Total output pins required: 1 Total bidirectional pins required: 0 Total logic cells required: 1 Total flipflops required: 0 Total product terms required: 9 Total logic cells lending parallel expanders: 0 Total shareable expanders in database: 8 Synthesized logic cells: 0/ 32 ( 0%) Device-Specific Information: c:\temp\cw2_5.rpt cw2_5 ** INPUTS ** Shareable Expanders Fan-In Fan-Out Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name 4 (1) (A) INPUT 0 0 0 0 0 1 0 a0 16 (11) (A) INPUT 0 0 0 0 0 1 0 a1 14 (10) (A) INPUT 0 0 0 0 0 1 0 a2 13 (9) (A) INPUT 0 0 0 0 0 1 0 d0 12 (8) (A) INPUT 0 0 0 0 0 1 0 d1 11 (7) (A) INPUT 0 0 0 0 0 1 0 d2 9 (6) (A) INPUT 0 0 0 0 0 1 0 d3 8 (5) (A) INPUT 0 0 0 0 0 1 0 d4 7 (4) (A) INPUT 0 0 0 0 0 1 0 d5 6 (3) (A) INPUT 0 0 0 0 0 1 0 d6 5 (2) (A) INPUT 0 0 0 0 0 1 0 d7 Code: s = Synthesized pin or logic cell t = Turbo logic cell + = Synchronous flipflop ! = NOT gate push-back r = Fitter-inserted logic cell Device-Specific Information: c:\temp\cw2_5.rpt cw2_5 ** OUTPUTS ** Shareable Expanders Fan-In Fan-Out Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name 41 17 B OUTPUT t 8 0 0 11 0 0 0 y Code: s = Synthesized pin or logic cell t = Turbo logic cell + = Synchronous flipflop ! = NOT gate push-back r = Fitter-inserted logic cell Device-Specific Information: c:\temp\cw2_5.rpt cw2_5 ** LOGIC CELL INTERCONNECTIONS ** Logic Array Block 'B': Logic cells placed in LAB 'B' +- LC17 y | | Other LABs fed by signals | that feed LAB 'B' LC | | A B | Logic cells that feed LAB 'B': Pin 4 -> * | - * | <-- a0 16 -> * | - * | <-- a1 14 -> * | - * | <-- a2 13 -> * | - * | <-- d0 12 -> * | - * | <-- d1 11 -> * | - * | <-- d2 9 -> * | - * | <-- d3 8 -> * | - * | <-- d4 7 -> * | - * | <-- d5 6 -> * | - * | <-- d6 5 -> * | - * | <-- d7 * = The logic cell or pin is an input to the logic cell (or LAB) through the PIA. - = The logic cell or pin is not an input to the logic cell (or LAB). Device-Specific Information: c:\temp\cw2_5.rpt cw2_5 ** EQUATIONS ** a0 : INPUT; a1 : INPUT; a2 : INPUT; d0 : INPUT; d1 : INPUT; d2 : INPUT; d3 : INPUT; d4 : INPUT; d5 : INPUT; d6 : INPUT; d7 : INPUT; -- Node name is 'y' -- Equation name is 'y', location is LC017, type is output. y = LCELL( _EQ001 $ VCC); _EQ001 = _X001 & _X002 & _X003 & _X004 & _X005 & _X006 & _X007 & _X008; _X001 = EXP( a0 & a1 & !a2 & d3); _X002 = EXP( a0 & a1 & a2 & d7); _X003 = EXP( a0 & !a1 & a2 & d5); _X004 = EXP(!a0 & a1 & a2 & d6); _X005 = EXP( a0 & !a1 & !a2 & d1); _X006 = EXP(!a0 & a1 & !a2 & d2); _X007 = EXP(!a0 & !a1 & a2 & d4); _X008 = EXP(!a0 & !a1 & !a2 & d0); -- Shareable expanders that are duplicated in multiple LABs: -- (none) Project Information c:\temp\cw2_5.rpt ** COMPILATION SETTINGS & TIMES ** Processing Menu Commands ------------------------ Design Doctor = off Logic Synthesis: Synthesis Type Used = Standard Default Synthesis Style = NORMAL Logic option settings in 'NORMAL' style for 'MAX7000' family DECOMPOSE_GATES = on DUPLICATE_LOGIC_EXTRACTION = on MINIMIZATION = full MULTI_LEVEL_FACTORING = on NOT_GATE_PUSH_BACK = on PARALLEL_EXPANDERS = off REDUCE_LOGIC = on REFACTORIZATION = on REGISTER_OPTIMIZATION = on RESYNTHESIZE_NETWORK = on SLOW_SLEW_RATE = off SOFT_BUFFER_INSERTION = on SUBFACTOR_EXTRACTION = on TURBO_BIT = on XOR_SYNTHESIS = on IGNORE_SOFT_BUFFERS = off USE_LPM_FOR_AHDL_OPERATORS = off Other logic synthesis settings: Automatic Global Clock = on Automatic Global Clear = on Automatic Global Preset = on Automatic Global Output Enable = on Automatic Fast I/O = off Automatic Register Packing = off Automatic Open-Drain Pins = on Automatic Implement in EAB = off One-Hot State Machine Encoding = off Optimize = 5 Default Timing Specifications: None Cut All Bidir Feedback Timing Paths = on Cut All Clear & Preset Timing Paths = on Ignore Timing Assignments = on Functional SNF Extractor = off Linked SNF Extractor = off Timing SNF Extractor = on Optimize Timing SNF = off Generate AHDL TDO File = off Fitter Settings = NORMAL Smart Recompile = off Total Recompile = off Interfaces Menu Commands ------------------------ EDIF Netlist Writer = off Verilog Netlist Writer = off VHDL Netlist Writer = off Compilation Times ----------------- Compiler Netlist Extractor 00:00:00 Database Builder 00:00:00 Logic Synthesizer 00:00:00 Partitioner 00:00:01 Fitter 00:00:00 Timing SNF Extractor 00:00:00 Assembler 00:00:00 -------------------------- -------- Total Time 00:00:01 Memory Allocated ----------------- Peak memory allocated during compilation = 3,597K